The technology described herein relates to voltage generation circuits, analog-to-digital conversion circuits, solid-state imaging devices, and imaging apparatuses.
Solid-state imaging devices having a resolution of as high as ten million pixels or more have been in practical use, and the cell size of a photoelectric conversion element has been increasingly reduced.
In order to achieve such a high-resolution solid-state imaging device, various techniques of reading a signal from a MOS image sensor have been proposed. In a conventional solid-state imaging device, for low noise and high speed, a pixel signal is detected by correlated double sampling (CDS) which uses a reset component and a data component (=the reset component+a signal component) which are digital signals obtained by analog-to-digital conversion using an A/D converter provided for each column.
In recent years, in addition to high resolution, the ability to perform high-speed shooting with high sensitivity has been demanded of solid-state imaging devices, and therefore, a further reduction in noise has been desired.
In general, noise occurring in solid-state imaging devices is roughly divided into two types, fixed pattern noise (FPN) and random noise. For FPN, since noise occurs in particular columns or pixels specific to each device, most of the noise can be removed by a correction technique which is optimized for each device using, for example, a digital signal processor (DSP) connected to an output of the solid-state imaging device.
On the other hand, random noise includes random noise which occurs mainly in the amplification transistors of pixels and randomly in the entire screen, and random horizontal noise which occurs mainly in an analog processing circuit provided in the vicinity of an imaging region. Since the noise level of random noise is not uniform, i.e., is random, it is difficult to correct the noise for each device.
In general, random noise is difficult to visually recognize, while random horizontal noise is easy to visually recognize. Therefore, specifically, random horizontal noise needs to be reduced to a level which is about 1/10 of the level of random noise occurring in the amplification transistor.
FIG. 10 is a circuit diagram showing a conventional voltage generation circuit 127 described in U.S. Pat. No. 6,956,413. The conventional voltage generation circuit 127 includes a DAC 127a and a control circuit 127b. The DAC 127a outputs a multi-level voltage reference signal RAMP using a ladder resistor circuit including ladder resistors R1-RN connected to a current varying circuit 127f, and switches SW0-SWN connected to taps between the ladder resistors. Note that Vtop shown in FIG. 10 indicates a top voltage of the ladder resistor circuit, and varies depending on a current value which varies depending on a signal CNG1. The control circuit 127b receives a signal CN4 and a clock signal CK0.